PLL03A
PLL08A
PLL Frequency Synthesizer
Overview
This 27 MHz band, PLL frequency synthesizer LSI chip is designed specifically for CB transceivers.
The integrated circuit`s incorporates PLL circuitry and a controller for CB applications on a single CMOS chip.
This PLL-circuit use a 7 bit ROM programmable divide-by-N counter. The ROM-table is programmed from factory to 40 channels.
| Pin | Name | Description |
|---|
| 1 | Vcc | Positive Supply Voltage |
| 2 | RI | Referency Oscillator Input |
| 3 | LD1 | |
| 4 | LD2 | |
| 5 | LD3 | |
| 6 | PD | Phase Detector Output |
| 7 | T/R | Transmit=HIGH Receive=LOW |
| 8 | F in | VCO Frequency Input |
| 9 | P6 | Programmable input 6 |
| 10 | P5 | Programmable input 5 |
| 11 | P4 | Programmable input 4 |
| 12 | P3 | Programmable input 3 |
| 13 | P2 | Programmable input 2 |
| 14 | P1 | Programmable input 1 |
| 15 | P1 | Programmable input 0 |
| 16 | GND | Ground |
Programming Chart for
PLL03A (U.S. - AM)
PLL08A (EEC - FM)
| Channel | RX
Divided by | TX
Divided by |
|---|
| 1 | 1206 | 1297 |
| 2 | 1208 | 1299 |
| .. | .... | .... |
| 22 | 1258 | 1349 |
| .. | .... | .... |
| 40 | 1294 | 1385 |
NOTES:
1. Special divided by 2 circuit in TX mode change Referency Divider output to 2.5kHz steps.
2. 91-count upshifts on TX provides 455kHz offset for receiver IF mixing when VCO frequency is doubled.
3. As the chip cannot divide VCO directly, they are down-mixed with the 10.240MHz Referency Oscillator signal, produsing 6MHz outputs (RX Mode) and 3MHz outputs (TX Mode) into dividers. Standard 16MHz VCO is used.
4. PLL08A contains only the first 22 FCC channels for EEC use; otherwise both chip are identical.
Example of VCO Determination, Channel 1:
1206 x 5kHz + 10.240MHz = 16.270MHz (RX-Mode)
1297 x 2.5kHz + 10.240MHz = 13.4825MHz (TX-Mode)
(13.4825MHz x 2 = 26.965MHz)
This counter shows the number of hits since the
29th January 2000
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